Hello, I'm looking for a timing diagram that shows the 1024 bit (bit-parallel) read-out bus from a JESD235B compliant 3D stack ( HBM 3D stack) and all relevant control strobes. Has anyone seen such a timing diagram ? I'm aware of the Xilinx AXI-HBM memory controller ( Virtex-Ultrascale, Versal-Ultrascale) but I want the raw JESD235B timing diagram for reading out 1024 bits in 1 clock cycle. Does this basic timing diagram exist in open-docs space ... HBM JESD235B 1024 bit read-out bus Weiterlesen...
